Accelerator-Based Architectures for Wireless Sensor Network Applications

Growing power consumption threatens the explosive growth that the semiconductor industry has sustained over the last several decades. While the number of transistors continues to double every process technology generation, the slowing of constant field scaling has caused power density to increase limiting clock frequency. To combat these trends, designers must get more performance from each transistor switch. Technology companies are applying microprocessors to a growing diversity of applications that are increasingly mobile and untethered from the power grid. One such domain is the emerging area of wireless sensor networks (WSNs) where, because nodes are often deeply embedded in an environment, power consumption is the primary design constraint. This dissertation explores the challenges of designing in a power-constrained era through the development of a model we call Navigo and the design and implementation of an accelerator-based architecture for WSNs. We designed Navigo to aid in early architecture exploration as an alternative to the spreadsheets and back-of-theenvelope calculations that planners use to guide future designs. The results show that, even under ideal conditions, multicore processors will not achieve the performance gains necessary to maintain growth. This dissertation shows that if an increas-